1. Field of the Invention
This invention is in the field of integrated circuits having internal masters and methods therefor and, more particularly, is a system having processor monitoring capability of an integrated circuit's buried, internal bus for use with a plurality of internal masters and a method therefor.
2. Description of the Related Art
The general field of concern here deals with Integrated Circuits (hereafter "IC(s)") having a plurality of internal masters connected to a corresponding plurality of external devices. In such systems, one or more of the external devices at some point need to send data to memory for use by a processor, and a given external device's corresponding internal master assists in this process. Typically, these internal masters share a bus from which an external device's data is delivered to the memory; however, before a given internal master may have use of this bus, it must request and then be granted access to the bus. In the past, this bus was "visible" to the processor. In other words, the processor could monitor what was happening on the bus.
Later, as technology advanced and the sizes of internal masters continued to shrink, they were able to be located on an IC chip, which also included the internal masters' communication bus, the internal masters' arbitor logic, and possibly other IC logic, not pertinent to the discussion here. Advances in technology are generally beneficial; however, as is the case here, they sometimes also have drawbacks. In particular, the reduced size of internal masters permitted them to be included with their associated bus and arbitor logic on the same IC, and this reduction in system real estate was, of course, technologically beneficial. The inherent drawback in this advanced system arrangement resulted from the fact that the internal masters' bus became "buried" or "invisible" to the processor. That is, unlike in the past when internal masters were relatively large and therefore had to be located on their own IC such that their bus was "visible" to the processor, now the internal masters' bus was no longer able to be connected to the processor for monitoring purposes. This is a critical aspect of the system which is the subject of this patent disclosure. More specifically, the system of interest here involves an "internal, buried bus" which is generally defined for the purpose of this patent disclosure as a bus for use by the internal masters of the system. Moreover, this bus is located on or "internal to" the IC chip containing the internal masters and typically also their arbitor logic. This "internal, buried bus" is "buried" in the sense that it has no direct connection to the processor for the purpose of monitoring the status of the bus. Lastly, this "buried, internal bus" (hereafter more simply the buried, internal bus or just bus) is used to transmit address/data type information to and/or from the internal masters.
One might fairly ask the question of how having an internal, buried bus presents a problem. The problem is called "hogging" and this is a term well known to those skilled in the art to refer to the situation where an internal master is granted control of the internal, buried bus, and refuses to release control. This hogging problem can occur from either software or hardware problems with the suspect internal master; however, the end result is typically that the IC chip would stop functioning without displaying any error indication. For example, assume that a system has five internal masters, each needing to have control of the internal, buried bus to do their jobs for 20 percent of a given period of time. Now, assume that one of the five internal masters has control of the bus; however, due to some hardware of software problem, the internal master cannot perform its full task within its allotted time slot comprising 20 percent of the work period. Thus, this internal master (i.e., the "hog") will exceed its designated time to complete its given task, and assuming that, at some later time, it relinquishes control of the bus, there will not be enough remaining work period time for the other internal masters to complete their respective tasks. As a result, the system will ultimately lock up and data will be lost. This problem could be alleviated if the processor had access to the internal, buried bus, because it could then monitor which internal masters have control of the bus, how long they have control of it, and then interrupt operation of hogging internal masters.
Therefore, there existed a need to provide a system having processor monitoring capability of an integrated circuit's buried, internal bus for use with a plurality of internal masters and a method therefor. Moreover, this system and method further needs, and is able, to control certain aspects of the operation of each of the internal masters.